The present invention relates generally to semiconductor wafers, and, more particularly, to a method of testing in parallel integrated circuits formed on the wafer.
In the design and fabrication of integrated circuits, individual circuits are designed used Electronic Design Automation (EDA) tools. When a design is completed (logic design, layout, simulation, etc.), the design is taped out, which means the design is saved in a form that can be used by a wafer fabrication facility to form an integrated circuit of the design on a semiconductor wafer. FIG. 1A is a simplified plan view of an example of an integrated circuit 10 that has been taped out. The integrated circuit 10 includes a plurality of input and output (I/O) pads 12, which includes power and ground pads, as is known in the art.
After the design is taped out, multiple instances of the circuit 10 are formed on a semiconductor wafer, with the individual instances known as dies. FIG. 1B shows a plurality of the integrated circuits 10 or dies as are typically manufactured with an array of identical dies formed on the wafer. The integrated circuits 10 include I/O or bond pads 12 and probe pads 14 that are used for testing the integrated circuits 10.
Once fabricated, the dies are preliminary tested to identify potentially fault free dies from defective dies. For convenience, such preliminary tests are performed before separating the dies from each other by dicing. As shown in FIG. 1C, these preliminary tests are performed using a test card 16 that has probes (pins) 18, with the probes 18 being placed in contact with the probe pads 14 on the integrated circuits 10.
Probe testing is inherently slow because it is a physical process in which the probes 18 are serially moved from test pads 14 on each die 10 to perform a sequence of tests. Testing times have been reduced by testing multiple dies on the wafer in parallel by using test cards with sets of probes. FIG. 1C shows 3 dies being tested at the same time. However, parallel testing of dies is becoming more complex as the number of die bond pads increases and probe pads get smaller. The industry has been addressing these issues by adding more probe pins and tester channels to the testers. However, more complexity and more tester channels equates to higher cost. Also, during probe testing, contact between the test probes and respective test pads results in a force being applied to the active surface of the integrated circuits under test. If this force is excessive, damage may occur to at least some of the integrated circuits being tested.
Therefore, it is an object of the present invention to alleviate at least one of the problems associated with testing dies formed on a wafer prior to dicing.